Network Function of a Circuit
Fast Decoupled and DC Powerflow
Buffers: Buffer Capacity
Norton Equivalent Circuits
Buffer Effectiveness
Block Diagram Reduction
You might also read
Articles linked to this work by shared authors, journal, and citation graph.
Updated: Aug 8, 2025

Large Scale Energy Efficient Sensor Network Routing Using a Quantum Processor Unit
Published on: September 8, 2023
Savvas Savva1, Konstantinos Tatas2, Costas Kyriacou2
1Department of Electrical Engineering, Computer Engineering and Informatics, Frederick University, 1036 Nicosia, Cyprus.
This study presents a novel 3D network-on-chip (NoC) router combining buffered and bufferless designs. It achieves performance and area gains using approximate priority comparison for efficient flit deflection.
Area of Science:
Background:
Purpose of the Study:
Main Methods:
Main Results:
Conclusions: