Hotspots Reduction for GALS NoC Using a Low-Latency Multistage Packet Reordering Approach

Area of Science:

• Computer Engineering
• VLSI Design
• Network-on-Chip Architectures

Background:

• Globally Asynchronous Locally Synchronous (GALS) Networks-on-chip (NoC) enable multipath routing, increasing bandwidth but causing out-of-order packet delivery.
• Packet reordering is crucial for Quality of Service (QoS) in NoCs, but traditional methods using local reorder buffers create hotspots, leading to chip aging and failures.

Purpose of the Study:

• To address the limitations of traditional packet reordering in GALS NoCs.
• To propose a novel approach that reduces transmission latency and alleviates on-chip hotspots.
• To improve the thermal efficiency and hardware resource utilization of NoC systems.

Main Methods:

• Introduction of a multistage packet reordering (MPR) approach.
• Implementation of a multistage reordering buffer (MRB) by reusing existing channel buffers.
• Evaluation of the proposed MPR approach through experimental analysis.

Main Results:

• The proposed MPR approach effectively reduces transmission latency compared to traditional methods.
• Significant reduction in on-chip hotspots was observed, mitigating chip aging concerns.
• Improved thermal efficiency and reduced hardware resource consumption were achieved.

Conclusions:

• The multistage packet reordering (MPR) approach offers a viable solution for managing out-of-order packets in GALS NoCs.
• Reusing channel buffers for multistage reordering (MRB) is an efficient strategy for enhancing NoC performance and reliability.
• The MPR method presents a promising direction for designing energy-efficient and robust NoC architectures.