Presynaptic spike-driven plasticity based on eligibility trace for on-chip learning system.

Area of Science:

• Neuroscience
• Computer Engineering
• Artificial Intelligence

Background:

• Recurrent Spiking Neural Networks (RSNNs) excel at spatio-temporal learning using Backpropagation Through Time (BPTT).
• BPTT's high computational and memory demands hinder practical on-chip implementation of RSNN learning systems.
• Field Programmable Gate Arrays (FPGAs) offer a potential platform for efficient neural network hardware.

Purpose of the Study:

• To develop a high-efficiency RSNN learning system deployable on FPGAs.
• To overcome the limitations of BPTT for on-chip RSNN applications.
• To reduce the resource and memory footprint of on-chip learning.

Main Methods:

• Implemented a presynaptic spike-driven plasticity architecture utilizing eligibility traces.
• Integrated Leaky Integrate-and-Fire (LIF) and adaptive LIF (ALIF) neuron models within the RSNN on FPGA.
• Optimized synaptic weight updates by storing only the latest presynaptic spike timestamps, avoiding temporal unfolding.

Main Results:

• Significantly reduced resource utilization (LUTs, registers) and dynamic power consumption in synaptic modules.
• Demonstrated reduced buffer size requirements for the on-chip learning system.
• Achieved high efficiency in terms of resources and energy, with accurate task performance on FPGA-implemented RSNNs.

Conclusions:

• The presynaptic spike-driven architecture enables efficient on-chip learning for RSNNs on FPGAs.
• This approach effectively addresses data congestion issues in large-scale learning system buffers.
• The developed system offers a practical solution for resource-constrained, energy-efficient AI hardware.