A 16-Channel Low-Power Neural Connectivity Extraction and Phase-Locked Deep Brain Stimulation SoC

Area of Science:

• Biomedical Engineering
• Neuroscience
• Integrated Circuit Design

Background:

• Deep brain stimulation (DBS) shows promise for regulating abnormal brain connectivity in neurological and psychiatric disorders.
• Phase-locked DBS requires precise measurement of neural activity and efficient stimulation control.

Purpose of the Study:

• To develop a low-power System-on-Chip (SoC) integrating neural connectivity extraction and phase-locked DBS capabilities.
• To enable energy-efficient and accurate real-time monitoring and modulation of brain activity.

Main Methods:

• A 16-channel low-noise analog front-end (AFE) for local field potential (LFP) recording.
• A novel low-complexity phase estimator and neural connectivity processor.
• A four-channel charge-balanced neurostimulator triggered by neural biomarkers.
• Fabrication in 65-nm CMOS technology.

Main Results:

• The SoC achieves a silicon area of 2.24 mm² and consumes 60 μW.
• Demonstrated over 60% power saving in neural connectivity extraction compared to existing methods.
• Successfully performed multi-channel LFP recording, real-time phase and connectivity extraction, and phase-locked stimulation in rats.

Conclusions:

• The developed SoC offers a power-efficient solution for advanced neural monitoring and closed-loop deep brain stimulation.
• This technology has the potential to improve therapeutic outcomes for various brain disorders by enabling precise, adaptive stimulation.