FPGA-based 4 × 29.4912 Gbit/s PS-PAM4 signal transmission with a low-complexity probabilistic shaping scheme

In this experiment, we demonstrate a real-time intensity modulation and direct detection (IM/DD) system based on a field programmable gate array (FPGA). For high-speed parallel signal processing, we propose and implement the simplified parallel-constant modulus algorithm (CMA) and decision-directed least mean square (DDLMS) equalizers with low complexity and low latency. Moreover, the bit-class probabilistic shaping (PS) scheme is adopted with very few hardware resources. The digital signal processing (DSP) steps are implemented in the XCVU9P-FLGB2104-2-I Xilinx FPGA with a clock frequency of 230.4 MHz. Based on the experimental results, 4 × 29.4912 Gbit/s PS-pulse amplitude modulation (PAM4) signals can be successfully transmitted over 25 km of standard single-mode fiber (SSMF) while satisfying the hard-decision forward error correction (HD-FEC) threshold at 3.8 × 10^-3. Compared with the uniformly distributed PAM4 signal, the low-complexity PS scheme can improve the receiver sensitivity by more than 1 dB.