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Author Spotlight: Enhancement of Salient Object Detection for Smart Grid Applications

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Published on: December 15, 2023

Parameterizable Design on Convolutional Neural Networks Using Chisel Hardware Construction Language.

Mukesh Chowdary Madineni¹, Mario Vega¹, Xiaokun Yang¹

¹University of Houston-Clear Lake, Houston, TX 77058, USA.

|March 29, 2023

Summary

This study introduces a parameterizable design generator for convolutional neural networks (CNNs) using Chisel hardware construction language (HCL). The 32-bit design offers optimal hardware performance on FPGAs, balancing accuracy and cost.

Keywords:

Chisel HCL FPGA Verilog HDL convolutional neural network (CNN)register–transfer level

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Deep Neural Networks for Image-Based Dietary Assessment

Deep Neural Networks for Image-Based Dietary Assessment

Published on: March 13, 2021

Area of Science:

Computer Engineering
Hardware Acceleration
Artificial Intelligence

Background:

Convolutional Neural Networks (CNNs) are computationally intensive.
Efficient hardware implementation of CNNs is crucial for real-time applications.
Existing hardware design methods may lack flexibility for diverse requirements.

Purpose of the Study:

To develop a parameterizable design generator for CNNs using Chisel HCL.
To enable the creation of multiple Register-Transfer Level (RTL) implementations.
To meet varying accuracy and hardware cost constraints.

Main Methods:

Utilized Chisel hardware construction language (HCL) for design generation.
Parameterized structural aspects like streaming width, pooling type, and floating-point precision.
Evaluated generated RTL designs (16-bit, 32-bit, 64-bit, 128-bit) on Field-Programmable Gate Arrays (FPGAs).

Main Results:

Generated multiple RTL implementations for CNNs.
The 32-bit design demonstrated optimal hardware performance on FPGAs.
Performance was assessed based on accuracy, FPGA slice count, and power dissipation.

Conclusions:

The parameterizable generator facilitates efficient RTL design for CNNs.
The 32-bit configuration provides a balanced trade-off for hardware performance.
The approach is extensible to other neural network architectures.