Search research articles

ABOUT JoVE

Overview Leadership Blog JoVE Help Center

AUTHORS

Publishing Process Editorial Board Scope & Policies Peer Review FAQ Submit

LIBRARIANS

Testimonials Subscriptions Access Resources Library Advisory Board FAQ

RESEARCH

JoVE Journal Methods Collections JoVE Encyclopedia of Experiments Archive

EDUCATION

JoVE Core JoVE Business JoVE Science Education JoVE Lab Manual Faculty Resource Center Faculty Site

Terms & Conditions of Use

Related Concept Videos

MOS Capacitor

MOS Capacitor

A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...

Capacitor With A Dielectric

Capacitor With A Dielectric

Parallel plate capacitors consist of two conducting plates separated by a certain distance. However, it is mechanically difficult to hold the large plates parallel to each other without actual contact. Hence, a dielectric layer is commonly placed between the plates, which provides an easy solution for holding the plates together with a small gap and increases the capacitance of the capacitor.
Dielectrics are non-conducting materials with no free or loosely bound electrons. When a dielectric is...

MOSFET: Enhancement Mode

MOSFET: Enhancement Mode

Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...

Dielectric Polarization in a Capacitor

Dielectric Polarization in a Capacitor

The presence of a dielectric medium in a capacitor not only changes the voltage and capacitance but also affects the electric field. In general, dielectrics can be of two types: polar and nonpolar. In a polar dielectric, the positive and negative charges in the molecules are separated by a distance and hence have a permanent dipole moment. In contrast, no such charge separation exists in a nonpolar dielectric, however the nonpolar molecules get polarized in the presence of an external electric...

Biasing of Metal-Semiconductor Junctions

Biasing of Metal-Semiconductor Junctions

Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...

Design Example: Capacitance Multiplier Circuit

Design Example: Capacitance Multiplier Circuit

In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by

Same author

Amphibian-inspired neuromorphic dynamic vision systems based on ferroelectric field-effect transistor.

Nature communications·2026

Same author

Optical metasurfaces for general vision processing on the edge.

Nature·2026

Same author

High encoding-sensitivity vision sensor with complementary nonlinear neuromorphic computing.

Nature communications·2026

Same author

Three-Dimensional Garment Architectures for Tactile Embodied Intelligence.

Advanced materials (Deerfield Beach, Fla.)·2026

Same author

Biomimetic-voltage nitride-enhanced memristor arrays for femtojoule in-memory biosignal processing.

Nature communications·2026

Same author

Artificial plateau neurons with in-situ spike-malleability for rhythmic quadrupedal locomotion.

Nature communications·2026

Search research articles

Related Experiment Video

Updated: Aug 4, 2025

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Published on: August 28, 2018

Carrier Modulation in 2D Transistors by Inserting Interfacial Dielectric Layer for Area-Efficient Computation.

Zheng Bian¹, Jialei Miao¹, Tianjiao Zhang¹

¹School of Micro-Nano Electronics, Hangzhou Global Scientific and Technological Innovation Centre, Zhejiang University, 38 Zheda Road, Hangzhou, 310027, China.

Small (Weinheim an Der Bergstrasse, Germany)

|April 3, 2023

Summary

This summary is machine-generated.

Researchers developed a new method to control carrier type in tungsten diselenide (WSe2) transistors using hexagonal boron nitride (h-BN). This breakthrough enables highly efficient, area-saving logic circuits with fewer transistors.

Keywords:

2D materials WSe 2 carrier modulation double-gate transistors logic gates

More Related Videos

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Published on: August 2, 2019

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures

Published on: December 5, 2015

Related Experiment Videos

Last Updated: Aug 4, 2025

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Published on: August 28, 2018

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Published on: August 2, 2019

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures

Published on: December 5, 2015

Area of Science:

Materials Science
Condensed Matter Physics
Nanotechnology

Background:

Two-dimensional (2D) materials offer excellent gate control for electronic circuits.
Dopant-induced scattering hinders carrier transport in 2D materials, limiting device performance.
Effective and non-destructive carrier modulation is crucial for advanced 2D electronics.

Purpose of the Study:

To devise a strategy for controlling carrier polarity in tungsten diselenide (WSe2) field-effect transistors (FETs).
To explore the use of hexagonal boron nitride (h-BN) as an interfacial dielectric layer for polarity modulation.
To demonstrate the potential for area-efficient logic circuits using this novel approach.

Main Methods:

Fabrication of WSe2 FETs with varying thicknesses of h-BN as the gate dielectric.
Electrical characterization to analyze carrier type and transport properties.
Implementation of WSe2 transistors in single-transistor logic gates (NOR, AND, XNOR) and half-adder circuits.

Main Results:

Carrier type in WSe2 FETs was successfully switched from hole to electron by modulating h-BN thickness.
Demonstrated versatile single-transistor logic gates (NOR, AND, XNOR).
Achieved a half-adder circuit using only two transistors, an 83.3% reduction compared to static Silicon CMOS technology.

Conclusions:

The h-BN interfacial layer provides effective and non-destructive carrier polarity control in WSe2 FETs.
This method significantly enhances area efficiency in logic computation.
The unique carrier modulation approach is broadly applicable to 2D logic gates and circuits.