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Updated: Jul 31, 2025
07:45
Quasi-light Storage for Optical Data Packets
Published on: February 6, 2014
10.9K
FPGA-based burst-error performance analysis and optimization of regular and irregular SD-LDPC codes for 50G-PON and
Optics Express
|May 9, 2023
Summary
We experimentally evaluated regular and irregular low-density parity-check (LDPC) codes for 50G-PON systems. Techniques like interleaving improved bit error rate (BER) performance against burst errors in 50-Gb/s upstream signals.
Area of Science:
- Telecommunications Engineering
- Digital Communications
- Error Correction Coding
Background:
- The 50G-PON standard requires robust error correction for high-speed upstream signals.
- Low-density parity-check (LDPC) codes are candidates for this standard, but their performance under burst errors needs evaluation.
- Burst errors, common in optical communication channels, can significantly degrade system performance.
Purpose of the Study:
- To experimentally evaluate the burst-error performance of regular and irregular LDPC codes for 50G-PON.
- To assess the effectiveness of specific techniques in mitigating burst errors for 50-Gb/s upstream signals.
Main Methods:
- Experimental measurements using Field-Programmable Gate Arrays (FPGA).
- Evaluation of both regular and irregular LDPC code structures.
- Implementation of intra codeword interleaving and parity-check matrix rearrangement.
Main Results:
- Demonstrated improved bit error rate (BER) performance under burst errors.
- Quantified performance gains for approximately 44-nanosecond duration burst errors.
- Validated the effectiveness of the applied techniques for 50-Gb/s upstream signals.
Conclusions:
- Intra codeword interleaving and parity-check matrix rearrangement effectively enhance LDPC code performance against burst errors.
- The evaluated LDPC codes show promise for reliable operation in 50G-PON systems despite bursty channel conditions.
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