A Highly Pipelined and Highly Parallel VLSI Architecture of CABAC Encoder for UHDTV Applications

Area of Science:

• Computer Science
• Electrical Engineering
• Information Technology

Background:

• Expansion of video data in Internet of Things (IoT) devices necessitates efficient video codecs.
• Context Adaptive Binary Arithmetic Coding (CABAC) is a critical but bottlenecked entropy coding module in standards like HEVC/H.265 and VVC/H.266.
• CABAC's inherent data dependencies cause pipeline stalls, limiting throughput.

Purpose of the Study:

• To address the throughput bottleneck in CABAC caused by data dependencies.
• To enhance the efficiency of video compression for IoT applications and high-resolution video streaming.
• To reduce the computational overhead and latency associated with CABAC in modern video coding standards.

Main Methods:

• Proposed a prediction-based context model prefetching strategy to eliminate memory access latency.
• Introduced multi-result context model update (MCMU) to reduce critical path delay.
• Implemented pre-range update, pre-renormalize techniques, and variable bypass bin incorporation (VBBI) for parallel processing.
• Developed a quad-loop cache for improved data interaction between entropy encoder and other modules.

Main Results:

• The pipeline architecture reduced coding time by up to 45.66% due to eliminated stalls.
• The parallel architecture saved 29.25% of coding time due to model updates (at QP=22).
• Achieved a throughput of 2191 Mbin/s, meeting 8K UHDTV requirements.
• Demonstrated higher hardware efficiency (Mbins/s per k gates) compared to existing architectures.

Conclusions:

• The proposed context model prefetching and parallel processing strategies effectively overcome CABAC's limitations.
• The optimized CABAC architecture significantly enhances video compression efficiency for demanding applications like 8K UHDTV.
• The developed techniques offer a substantial improvement in throughput and hardware efficiency for video codecs.