Power-Intent Systolic Array Using Modified Parallel Multiplier for Machine Learning Acceleration.

Area of Science:

• Computer Architecture
• Machine Learning Hardware
• VLSI Design

Background:

• Systolic arrays are crucial for machine learning (ML) accelerators, excelling at matrix multiplication.
• Current designs prioritize area and delay, with power optimization as a secondary concern.
• Existing power optimization methods often compromise area or delay performance.

Purpose of the Study:

• To propose a novel Power-Intent Systolic Array (PI-SA) for ML accelerators.
• To significantly reduce power consumption in systolic arrays without major area or delay trade-offs.
• To enhance the energy efficiency of ML hardware.

Main Methods:

• Implemented fine-grained power gating of the multiplication and accumulation (MAC) block multiplier within processing elements.
• Introduced a modified decomposition multiplier to reduce the size of the reduction tree.
• Replaced carry propagation adders with carry save adders in sub-multipliers to improve area and delay.

Main Results:

• Achieved up to 57% power reduction compared to baseline designs.
• Demonstrated up to 32% area improvement.
• Reported up to 6% delay reduction for varying accumulator bit-widths.

Conclusions:

• The proposed PI-SA effectively reduces power consumption in ML accelerators.
• The design achieves significant improvements in power, area, and delay.
• PI-SA offers a promising approach for energy-efficient ML hardware design.