Calibration-Free and Hardware-Efficient Neural Spike Detection for Brain Machine Interfaces.

Area of Science:

• Biomedical Engineering
• Neuroscience
• Implantable Devices

Background:

• Brain-machine interfaces (BMIs) are advancing neurological disorder treatments.
• Increasing channel counts in BMIs generate large datasets, demanding high bandwidth and power.
• On-implant data processing is crucial for managing bandwidth and power constraints.

Purpose of the Study:

• Develop a novel, hardware-efficient spike detection algorithm for intracortical BMIs.
• Create an adaptive algorithm requiring no external training for real-time applications.
• Benchmark the algorithm's performance against existing methods.

Main Methods:

• Developed a firing-rate-based spike detection algorithm.
• Validated the algorithm on a reconfigurable hardware (FPGA) platform.
• Implemented the algorithm in digital ASIC designs (65 nm and 0.18 μm CMOS).

Main Results:

• The 128-channel ASIC design (65 nm CMOS) uses 4.86 μW and occupies 0.096 mm².
• Achieved 96% spike detection accuracy on a synthetic dataset without prior training.
• Demonstrated adaptability, power efficiency, and scalability for chronic deployment.

Conclusions:

• The novel spike detection algorithm is hardware-efficient and suitable for real-time BMI applications.
• The algorithm effectively reduces bandwidth and power requirements for implanted systems.
• This technology supports the advancement of high-channel-count BMIs for neurological applications.