An Investigation of SILC Degradation under Constant Voltage Stress in PDSOI Devices

The stress-induced leakage current (SILC) degradation of partially depleted silicon in insulator (PDSOI) devices under constant voltage stress (CVS) was studied. Firstly, the behaviors of threshold voltage degradation and SILC degradation of H-gate PDSOI devices under constant voltage stress were studied. It was found that both the threshold voltage degradation and SILC degradation of the device are power functions of the stress time, and the linear behavior between SILC degradation and threshold voltage degradation is good. Secondly, the soft breakdown characteristics of the PDSOI devices were studied under CVS. Thirdly, the effects of different gate stresses and different channel lengths on the threshold voltage degradation and SILC degradation of the device were studied. The results showed SILC degradation of the device under positive CVS and SILC degradation of the device under negative CVS. The shorter the channel length of the device was, the greater the SILC degradation of the device was. Finally, the influence of the floating effect on the SILC degradation of the PDSOI devices was studied, and the experimental results showed that the degree of SILC degradation of the floating device was greater than that of the H-type grid body contact PDSOI device. This showed that the floating body effect can exacerbate the SILC degradation of PDSOI devices.