Approaching the mapping limit with closed-loop mapping strategy for deploying neural networks on neuromorphic...

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Architecture

Background:

• Decentralized manycore architectures are common in neuromorphic chips due to parallelism and memory locality.
• Deploying neural network models on these architectures faces challenges in resource utilization and processing efficiency due to fragmented memories and decentralized execution.

Purpose of the Study:

• To introduce the concept of a 'mapping limit' for resource saving in logical and physical mapping of neural networks onto neuromorphic hardware.
• To propose a novel closed-loop mapping strategy to enhance deployment efficiency.

Main Methods:

• Introduced the 'mapping limit' concept to define resource saving upper bounds.
• Developed a closed-loop mapping strategy involving asynchronous 4D model partitioning for logical mapping.
• Utilized a Hamilton loop algorithm (HLA) for physical mapping.

Main Results:

• Implemented the proposed mapping methods on the TianjicX neuromorphic chip.
• Demonstrated superior performance compared to existing methods.
• Achieved results that approach the defined mapping limit.

Conclusions:

• The proposed mapping limit concept and closed-loop strategy offer significant improvements in neural network deployment on neuromorphic hardware.
• These advancements can contribute to a general and efficient mapping framework for neuromorphic systems.