Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET

Area of Science:

• Semiconductor device physics and engineering.
• Advanced transistor technology and materials science.

Background:

• Planar MOSFET scaling limitations necessitate advanced device architectures.
• FinFET and Silicon-On-Insulator (SOI) are key post-planar MOSFET technologies.
• SiGe channels offer performance enhancement for SOI FinFET devices.

Purpose of the Study:

• To develop an optimization strategy for Germanium (Ge) fraction in SiGe channels of SGOI FinFET devices.
• To investigate the impact of varying Ge fraction on circuit performance and power consumption.

Main Methods:

• Device simulation of SGOI FinFET structures with varying Ge fractions.
• Circuit-level simulations using ring oscillator (RO) circuits.
• Analysis of static random-access memory (SRAM) cell performance.

Main Results:

• Altering the Ge fraction in SiGe channels significantly impacts SGOI FinFET device characteristics.
• Optimized Ge fractions lead to improved performance metrics in RO circuits.
• SRAM cell performance, including speed and power, is tunable via Ge fraction adjustment.

Conclusions:

• The Ge fraction in SiGe channels of SGOI FinFETs is a critical design parameter for performance tuning.
• A tailored optimization strategy for Ge fraction enables customized performance and power efficiency for diverse applications.
• This work provides a pathway for designing next-generation high-performance and low-power semiconductor devices.