A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction...

Area of Science:

• Materials Science
• Electrical Engineering
• Computer Engineering

Background:

• Non-volatile memory transistors (H-MTRs) are crucial for advanced computing.
• Controlling negative transconductance (NTC) is key for novel logic functionalities.
• Reconfigurable logic offers flexibility but faces challenges in stability and performance.

Purpose of the Study:

• To develop a new H-MTR with systematically controllable NTC characteristics.
• To implement a reconfigurable logic inverter (R-inverter) based on the novel H-MTR.
• To demonstrate a novel ternary/binary dynamic logic conversion-in-memory system.

Main Methods:

• Fabrication of H-MTRs with a drain-aligned floating gate for NTC control.
• Programming operations to achieve reliable transitions between NTC and non-NTC transfer curves.
• Implementation and testing of binary/ternary R-inverters and a serially-connected R-inverter chain.

Main Results:

• Demonstrated systematic control of NTC in H-MTRs via a drain-aligned floating gate.
• Achieved reliable transitions between N-shaped and current-increasing transfer curves.
• Implemented R-inverters with high static noise margins (85% binary, 59% ternary), long-term stability, and cycle endurance.
• Successfully demonstrated ternary/binary dynamic logic conversion-in-memory with a novel three-level logic output.

Conclusions:

• The developed H-MTR offers a new pathway for designing advanced memory and logic devices.
• The R-inverter exhibits superior performance for both binary and ternary logic operations.
• The demonstrated conversion-in-memory system presents a novel computing paradigm with potential for future logic applications.