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Related Concept Videos

Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

841
In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
841

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A minimum assumption approach to MEG sensor array design.

Andrey Zhdanov1,2, Jussi Nurminen3, Joonas Iivanainen4

  • 1BioMag Laboratory, HUS Diagnostic Center, Helsinki University Hospital and University of Helsinki, Helsinki, Finland.

Physics in Medicine and Biology
|June 29, 2023
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Summary
This summary is machine-generated.

This study redefines magnetoencephalographic (MEG) sensor array design as an engineering problem, focusing on accurate neuromagnetic field measurement. A new figure-of-merit quantifies sensor noise amplification, enabling optimized MEG sensor array design.

Keywords:
MEGchannel information capacityoptically pumped magnetometeroptimizationsensor arrayvector spherical harmonics

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Area of Science:

  • Biophysics
  • Biomedical Engineering
  • Neuroscience

Background:

  • Magnetoencephalography (MEG) traditionally focuses on neurobiological interpretability.
  • Sensor array design is crucial for accurate neuromagnetic field measurement.
  • Optimizing MEG sensor arrays requires a well-posed engineering approach.

Purpose of the Study:

  • To reformulate MEG sensor array design as an engineering problem focused on accurate neuromagnetic field measurement.
  • To develop a quantitative figure-of-merit for evaluating MEG sensor array performance.
  • To enable the optimization of MEG sensor array configurations.

Main Methods:

  • Utilizing the vector spherical harmonics (VSH) formalism.
  • Defining a figure-of-merit based on sensor noise amplification.
  • Applying nonlinear optimization methods like simulated annealing.

Main Results:

  • A mathematically rigorous figure-of-merit for MEG sensor array design was derived.
  • The figure-of-merit effectively quantifies sensor noise amplification.
  • Optimized sensor arrays demonstrated high channel information capacity.

Conclusions:

  • The proposed figure-of-merit provides a robust method for MEG sensor array design optimization.
  • This approach shifts the focus from neurobiological interpretability to engineering performance.
  • The work facilitates the development of superior MEG sensor arrays for brain research.