An OpenCL-Based FPGA Accelerator for Faster R-CNN.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Convolutional Neural Network (CNN)-based object detection algorithms, particularly Faster R-CNN, face challenges due to high computational and memory complexity.
• Existing hardware accelerator designs predominantly focus on one-stage detectors like YOLO, leaving a gap for efficient Faster R-CNN implementations.
• Field-Programmable Gate Arrays (FPGAs) offer a promising platform for custom hardware acceleration of complex deep learning models.

Purpose of the Study:

• To propose a software-hardware co-design scheme for implementing the Faster R-CNN object detection algorithm on FPGAs using OpenCL.
• To design an efficient, deep-pipelined FPGA hardware accelerator capable of supporting various backbone networks for Faster R-CNN.
• To optimize the Faster R-CNN algorithm for hardware implementation through techniques like fixed-point quantization and layer fusion.

Main Methods:

• Development of a deep-pipelined FPGA hardware accelerator tailored for Faster R-CNN.
• Implementation of a hardware-aware software algorithm including fixed-point quantization, layer fusion, and a multi-batch Regions of Interest (RoIs) detector.
• Utilization of OpenCL for software-hardware co-design and an end-to-end design space exploration scheme for performance and resource evaluation.

Main Results:

• The proposed FPGA accelerator achieved a peak throughput of 846.9 GOP/s at a working frequency of 172 MHz.
• Demonstrated a 10x inference throughput improvement compared to state-of-the-art Faster R-CNN accelerators.
• Achieved a 2.1x inference throughput improvement over one-stage YOLO accelerators.

Conclusions:

• The proposed software-hardware co-design scheme effectively addresses the computational and memory challenges of Faster R-CNN on FPGAs.
• The developed FPGA accelerator offers significant performance gains, making it a competitive solution for real-time object detection.
• This work advances the field of hardware acceleration for complex deep learning models, particularly for two-stage object detectors.