Hardware Trojan Mitigation Technique in Network-on-Chip (NoC).

Area of Science:

• Computer Engineering
• Cybersecurity
• Integrated Circuit Design

Background:

• Globalization in the semiconductor industry increases risks of hardware Trojans (HTs) in integrated circuits.
• Existing methods for HT detection and mitigation are insufficient for network-on-chip (NoC) architectures.
• Hardware Trojans pose a critical threat to chip security due to potential malicious modifications.

Purpose of the Study:

• To propose a collaborative countermeasure against hardware Trojans specifically targeting network-on-chip designs.
• To enhance the security of NoC routers against malicious modifications by disloyal employees or third-party vendors.
• To prevent unauthorized changes to the network-on-chip hardware design.

Main Methods:

• Implementation of a countermeasure to secure the network-on-chip hardware design.
• Utilizing a collaborative method involving flit integrity and dynamic flit permutation.
• Eliminating hardware Trojans inserted into the NoC router.

Main Results:

• The proposed method increases the number of received packets by up to 10% compared to existing techniques.
• Reduces average latency for hardware Trojans inserted in the flit's header, tail, and destination field by up to 14.7%, 8%, and 3%, respectively.
• Effectively eliminates hardware Trojans from the NoC router.

Conclusions:

• The proposed collaborative method offers a robust solution for securing network-on-chip designs against hardware Trojans.
• This approach significantly improves packet reception rates and reduces latency in the presence of HTs.
• The technique provides enhanced security for NoC hardware against internal and external threats.