SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Neuroscience

Background:

• Neuromorphic processors emulate brain principles for efficient, low-power computing.
• Existing designs often lack flexibility, leading to performance and memory inefficiencies with diverse neural network algorithms.

Purpose of the Study:

• To propose SENECA, a digital neuromorphic architecture balancing flexibility and efficiency.
• To demonstrate SENECA's capability for efficient mapping of various neural networks, on-device learning, and pre-post processing.

Main Methods:

• Designed SENECA with a hierarchical-controlling system featuring a flexible RISC-V controller and an optimized Loop Buffer controller.
• Implemented a flexible computational pipeline for diverse algorithmic deployments.
• Utilized a network-on-chip for scalable architecture.

Main Results:

• SENECA demonstrates improved energy and area efficiency compared to existing designs.
• A SENECA core occupies 0.47 mm² (GF-22 nm) and consumes 2.8 pJ per synaptic operation.
• Experimental results validate efficient mapping for various algorithms and highlight design trade-offs.

Conclusions:

• SENECA offers a highly efficient and programmable digital neuromorphic processor.
• The architecture effectively addresses the flexibility-efficiency trade-off in neuromorphic computing.
• The SENECA platform is available for academic research.