Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption
Related Experiment Video
Updated: Jul 24, 2025

Characterization of Anisotropic Leaky Mode Modulators for Holovideo
Published on: March 19, 2016
1Department of Information and Communication Engineering, Inha University, Incheon 22212, Republic of Korea.
Abstract:
The increasing ubiquity of big data and cloud-based computing has led to increased concerns regarding the privacy and security of user data. In response, fully homomorphic encryption (FHE) was developed to address this issue by enabling arbitrary computation on encrypted data without decryption. However, the high computational costs of homomorphic evaluations restrict the practical application of FHE schemes. To tackle these computational and memory challenges, a variety of optimization approaches and acceleration efforts are actively being pursued. This paper introduces the KeySwitch module, a highly efficient and extensively pipelined hardware architecture designed to accelerate the costly key switching operation in homomorphic computations. Built on top of an area-efficient number-theoretic transform design, the KeySwitch module exploited the inherent parallelism of key switching operation and incorporated three main optimizations: fine-grained pipelining, on-chip resource usage, and high-throughput implementation. An evaluation on the Xilinx U250 FPGA platform demonstrated a 1.6× improvement in data throughput compared to previous work with more efficient hardware resource utilization. This work contributes to the development of advanced hardware accelerators for privacy-preserving computations and promoting the adoption of FHE in practical applications with enhanced efficiency.
More Related Videos
Related Concept Videos
Parallel Processing
Phasor Arithmetics
When the derivative of a sinusoid is taken in the time domain, it transforms into its corresponding phasor multiplied by j-omega (jω) in the phasor domain, where j is the imaginary unit, and ω is the angular...
Clipper Circuit
The operation of a clipper circuit can be exemplified by analyzing a dual-clipper configuration setup that integrates two ideal diodes, each paired with a biasing...
Design Example: Capacitance Multiplier Circuit
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
Clamper Circuit
Within this circuit, the diode's orientation prompts the capacitor to charge up to the level of the most negative peak of the input signal. Upon reaching this state, the diode ceases to...
Block Diagram Reduction
The first step in this process is the identification and relocation of a branch point. A branch point, where a...

