Theoretical Upper and Lower Limits for Normalized Bandwidth of Digital Phase-Locked Loop in GNSS Receivers

Area of Science:

• Electrical Engineering
• Signal Processing
• Satellite Navigation

Background:

• Digital phase-locked loops (DPLLs) are crucial for Global Navigation Satellite System (GNSS) receivers.
• Accurate determination of loop noise bandwidth and coherent integration time is essential for DPLL design.
• Current design practices rely on approximate stability criteria for normalized bandwidth, which may not be universally applicable.

Purpose of the Study:

• To derive theoretical upper and lower limits for the normalized bandwidth of DPLLs in GNSS receivers.
• To provide a more precise method for setting DPLL parameters beyond general stability rules.
• To enhance the reliability and performance of GNSS receivers through improved DPLL design.

Main Methods:

• Investigated DPLL stability using z-plane root loci, considering digital integration methods and computational delay for the upper limit.
• Analyzed DPLL measurement error, including thermal noise, oscillator phase noise, and dynamic stress, for the lower limit.
• Utilized the carrier-to-noise density ratio threshold to determine the crossing point between measurement error and its threshold.

Main Results:

• Established theoretical upper and lower bounds for the normalized bandwidth of DPLLs in GNSS receivers.
• Demonstrated that actual limit points for normalized bandwidth vary with loop filter order and implementation.
• Identified a potential lower limit for normalized bandwidth that was not previously considered.

Conclusions:

• The derived theoretical limits offer a more rigorous approach to DPLL parameter selection in GNSS receivers.
• Accurate normalized bandwidth determination is critical for optimizing DPLL performance and receiver reliability.
• This research provides valuable insights for engineers designing robust GNSS receivers.