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Updated: Jul 23, 2025

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices
Published on: December 7, 2017
Evolution of type-II hetero-strain cylindrical-gate-all-around nanowire FET for exploration and analysis of enriched
Rasmita Barik1, Rudra Sankar Dhar2, Falah Awwad3
1Department of Electronics and Communication Engineering, National Institute of Technology Mizoram, Chaltlang, Aizawl, Mizoram, India.
Abstract:
The incubation of strained nano-system in the form of tri-layered structure as nanowire channel in the cylindrical-gate-all-around (CGAA) FET at 10 nm gate length is developed for the first time to keep abreast with the proposed 3 nm technology node of IRDS 2022. The system installs Type-II hetero-strain alignment in the channel attesting itself as the fastest operating device debasing the SCEs at nano regime. The ultra-thin strained-channel comprises of two cylindrical s-Si wells encompassing s-SiGe barrier in between, which enables improvement of carrier mobility by succumbing of quantum charge carriers in the region. This results in 2D charge centroid creation with cylindrical based circular Nano-system contemplating electrostatic potential difference leading to enriched electric field, current density and transconductance, while the gate-all-around architecture with increased gate controllability lowers leakage current, in the device. The 10 nm strained-channel CGAA astounded havoc ON current enhancements of ~ 20% over 22 nm strained CGAA, 57% over Si CGAA FET and 75% over proposed 3 nm technology node IRDS 2022 are accomplished. Hence, carrier mobility and velocity enriches instituting quasi-ballistic transport through the Nanowire channel, thereby augments in ~ 28% drain current so the 10 nm channel CGAA FET stands as the most suitable and improved device in nano regime.
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