A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS.

Area of Science:

• Electrical Engineering
• Signal Processing
• Integrated Circuit Design

Background:

• Wideband sampling receivers require high-performance analog-to-digital converters (ADCs) for accurate signal acquisition.
• Existing ADCs often face limitations in linearity, bandwidth, and power efficiency for demanding applications.

Purpose of the Study:

• To present a novel single-channel, 12-bit, 2 GS/s pipelined ADC architecture optimized for wideband sampling receivers.
• To improve sample linearity, extend operational bandwidth, and enhance overall ADC performance through innovative circuit design.

Main Methods:

• Implementation of a novel source follower input buffer with multiple feedback loops for enhanced linearity and bandwidth.
• Introduction of an improved two-stage charge pump amplifier topology to double the Gain Bandwidth Product (GBW) without increased power consumption.
• Employment of a multi-level dither strategy with a high-speed pseudorandom code generator for back-end ADC and background calibration.

Main Results:

• The prototype ADC, fabricated in a 40 nm CMOS process, achieves a Spurious-Free Dynamic Range (SFDR) of 68.24 dB at the Nyquist frequency with a 2 GS/s sampling rate.
• Demonstrated measurement results show a bandwidth exceeding 5 GHz.
• Achieved a high Schreier Figure of Merit (FOM) of 152.4 dB, indicating superior performance.

Conclusions:

• The proposed pipelined ADC architecture effectively addresses the challenges of wideband sampling, offering significant improvements in linearity and bandwidth.
• The innovative circuit techniques and calibration strategy result in a high-performance ADC suitable for advanced receiver systems.
• The fabricated prototype validates the design's potential for next-generation high-speed data conversion.