Inductive line tunneling FET using epitaxial tunnel layer with Ge-source and charge enhancement insulation

In this paper, we propose an inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET). The CEI ETL GS-iTFET allows full overlap between the gate and source regions, thereby enhancing the line tunneling. In addition, a germanium layer is introduced on the source side to form a heterojunction, effectively improving the device's conduction current. An ETL is incorporated to combat point tunneling leakage, resulting in a steeper subthreshold swing. Furthermore, a CEI consisting of Si₃N₄ is introduced between the germanium source and the Schottky metal, which effectively reduces carrier losses in the inversion layer and improves the overall device performance. This study presents a calibration-based approach to simulations, taking into account practical process considerations. Simulation results show that at V_D = 0.2 V, the CEI ETL GS-iTFET achieves an average subthreshold swing (SS_avg) of 30.5 mV/dec, an I_on of 3.12 × 10^-5 A/μm and an I_on/I_off ratio of 1.81 × 10¹⁰. These results demonstrate a significantly low subthreshold swing and a high current ratio of about 10¹⁰. In addition, the proposed device eliminates the need for multiple implantation processes, resulting in significant manufacturing cost reductions. As a result, the CEI ETL GS-iTFET shows remarkable potential in future low-power device competition.