High-Density Vertical Transistors with Pitch Size Down to 20 nm

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Vertical field-effect transistors (VFETs) offer a path to ultra-scaled devices by enabling vertical stacking.
• Fabricating high-density VFETs with small pitch sizes is challenging due to trade-offs between drain thickness and conductivity.

Purpose of the Study:

• To develop a simple approach for scaling VFET drain dimensions to sub-10 nm.
• To achieve record low pitch sizes for vertically stacked transistors.

Main Methods:

• A hybrid drain was created by combining 7 nm thick gold (Au) with monolayer graphene.
• The hybrid drain was van der Waals laminated onto a 3 nm thick channel.
• Gate stack scaling was performed to reduce VFET pitch size.

Main Results:

• The hybrid drain exhibited metallic behavior with low sheet resistance (≈100 Ω sq⁻¹).
• VFETs achieved a pitch size down to 20 nm with an on-state current of 730 A cm⁻².
• Three VFETs were vertically stacked within 59 nm, setting a record for low pitch size in vertical transistors.

Conclusions:

• The developed method successfully scales VFETs to sub-10 nm drain dimensions.
• This approach pushes the limits of VFET scaling and pitch size, enabling new possibilities for high-density vertical transistors and integrated circuits.