QuantLaneNet: A 640-FPS and 34-GOPS/W FPGA-Based CNN Accelerator for Lane Detection.

Area of Science:

• Computer Vision
• Autonomous Systems
• Deep Learning

Background:

• Lane detection is crucial for autonomous vehicles.
• Existing deep learning methods often require extensive post-processing or are too complex for real-time applications.

Purpose of the Study:

• To develop a lightweight convolutional neural network for efficient lane detection.
• To address limitations of segmentation-based approaches and complex model architectures.

Main Methods:

• Proposed a lightweight convolutional neural network with a simple lane representation output.
• Implemented a hardware accelerator on an FPGA (Virtex-7 VC707) using 8-bit data quantization, loop-unrolling, and pipelined computation.
• Achieved 93.53% accuracy on the TuSimple dataset.

Main Results:

• The proposed model achieves 93.53% accuracy on the TuSimple dataset.
• The FPGA implementation processes at 640 FPS with low power consumption (10.309 W).
• Demonstrated high computational throughput (345.6 GOPS) and energy efficiency (33.52 GOPS/W).

Conclusions:

• The lightweight network offers an effective solution for real-time lane detection in autonomous vehicles.
• Hardware acceleration significantly optimizes processing speed and power efficiency.
• The approach overcomes limitations of existing deep learning methods for lane detection.