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Aging Compensation in a Class-A High-Frequency Amplifier with DC Temperature Measurements
Josep Altet1, Xavier Aragones1, Enrique Barajas1
1Electronic Engineering Department, Universitat Politcnica de Catalunya-Barcelona Tech, 08034 Barcelona, Spain.
Sensors (Basel, Switzerland)
|August 26, 2023
Summary
This study introduces DC temperature measurements to monitor and counteract performance degradation in nanometric CMOS analog circuits caused by transistor aging. This method effectively restores amplifier gain, with one procedure achieving full restoration.
Area of Science:
- Electrical Engineering
- Materials Science
- Reliability Engineering
Background:
- Transistor aging in nanometric CMOS analog circuits causes performance degradation, threatening reliability.
- Extending circuit operating life requires monitoring and adjusting device bias during aging.
Purpose of the Study:
- To propose and validate DC temperature measurements as a method for monitoring circuit performance degradation.
- To demonstrate the use of temperature readings for automatically adjusting device bias and restoring degraded circuit performance.
Main Methods:
- Utilized DC temperature measurements near a high-frequency class-A power amplifier and differential temperature sensor.
- Implemented two distinct procedures for DC temperature measurements to track amplifier gain degradation.
- Developed an automated bias adjustment mechanism based on observed temperature readings.
Main Results:
- Accelerated aging degraded amplifier gain by up to 50%.
- DC temperature measurements successfully tracked amplifier gain degradation.
- One procedure restored amplifier gain to its original value, while the second achieved partial restoration.
Conclusions:
- DC temperature measurements offer a viable method for monitoring transistor aging effects in CMOS analog circuits.
- Automated bias adjustment based on temperature feedback can effectively restore degraded circuit performance.
- The proposed method enhances the operational lifespan and reliability of nanometric CMOS analog circuits.
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