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Photoelectric performance of InSe vdW semi-floating gate p-n junction transistor
Jinghui Wang1, Yipeng Wang2, Guojin Feng3
1Division of Thermophysics Metrology, National Institute of Metrology, Beijing 100029, People's Republic of China.
Abstract:
Semi-floating gate transistors based on vdW materials are often used in memory and programmable logic applications. In this paper, we propose a semi-floating gate photoelectric p-n junction transistor structure which is stacked by InSe/h-BN/Gr. By modulating gate voltage, InSe can be presented as N-type and P-type respectively on different substrates, and then combined into p-n junction. Moreover, InSe/h-BN/Gr device can be switched freely between N-type resistance and p-n junction. The resistance value of InSe resistor and the photoelectric properties of the p-n junction are also sensitively modulated by laser. Under dark conditions, the rectification ratio of p-n junction can be as high as 107. After laser modulation, the device has a response up to 1.154 × 104A W-1, a detection rate up to 5.238 × 1012Jones, an external quantum efficiency of 5.435 × 106%, and a noise equivalent power as low as 1.262 × 10-16W/Hz1/2. It lays a foundation for the development of high sensitivity and fast response rate tunable photoelectric p-n junction transistor.
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