Bilateral sidewall engineering Si_1-xGe_xiTFET for low power display application

In this work, we demonstrate the performance enhancement of bottom-gated inductive line-tunneling TFET (iTFET) through the integration of bilateral sidewall engineering with SiGe mole fraction variation, considering the feasibility of the fabrication process. We also employ a metal-semiconductor interface for carrier induction to improve theI_ON, resulting in a lower subthreshold swing average (S.S_avg). Using Sentaurus TCAD simulations, we show that the dominant current mechanism is line tunneling, and the hump effect is mitigated by using SiGe with different mole fractions on the sidewalls. Compared to conventional tunnel field-effect transistors, which require at least three doping processes and annealing, the proposed device requires only one doping process and utilizes the metal-semiconductor interface for carrier induction, significantly reducing the fabrication cost and thermal budget. These measurement based simulations show that theS.S_avgis improved to 21.5 mV dec^-1with anI_ON/I_OFFratio of 106 atV_D= 0.2 V. This is the first time that a TFT with a subthreshold swing of less than 60 mV dec^-1has been proposed, so it will save much more power in the future and displays with high energy efficiency can be realized and widely used in IoT applications.