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High-speed and energy-efficient asynchronous carry look-ahead adder.

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This summary is machine-generated.

This study introduces novel asynchronous carry look-ahead adders (CLAs) for faster and more energy-efficient computing. The block CLA (BCLA) design significantly optimizes performance metrics like delay, area, and power consumption.

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Area of Science:

  • Computer Engineering
  • Digital Circuit Design
  • VLSI Design

Background:

  • Addition is a critical arithmetic operation in processors.
  • High-speed and energy-efficient adder design is crucial for practical applications.
  • Asynchronous design offers potential advantages in speed and power.

Purpose of the Study:

  • To design and evaluate novel asynchronous carry look-ahead adders (CLAs).
  • To compare the performance of a standard CLA (SCLA) and a block CLA (BCLA).
  • To optimize adder designs for reduced cycle time, area, power, and energy consumption.

Main Methods:

  • Development of monotonic, dual-rail encoded CLAs using RZH and ROH protocols.
  • Implementation using 28-nm CMOS process technology.
  • Performance comparison of the proposed SCLA and BCLA against state-of-the-art asynchronous adders.

Main Results:

  • The proposed BCLA demonstrates significant improvements over the SCLA.
  • For a 32-bit addition, BCLA achieved up to 32.6% reduction in cycle time, 29% in area, 4.3% in power, and 35.5% in energy (RZH).
  • BCLA also showed reductions in cycle time and power/energy compared to other asynchronous adders.

Conclusions:

  • The novel asynchronous BCLA offers superior performance compared to SCLA and existing designs.
  • The proposed BCLA is a promising solution for high-speed and energy-efficient digital processing.
  • Asynchronous adders, particularly the BCLA, are key for advancing processor efficiency.