SEU Hardened D Flip-Flop Design with Low Area Overhead

Area of Science:

• Digital Electronics
• Integrated Circuit Design
• Radiation Hardening

Background:

• D flip-flops (DFFs) are fundamental to sequential logic but susceptible to single event upsets (SEUs) caused by high-energy particles due to internal cross-coupled inverters.
• SEUs can corrupt data stored in flip-flops, leading to errors in digital circuits.

Purpose of the Study:

• To propose a novel D flip-flop structure with enhanced capability for single event upset (SEU) fortification.
• To evaluate the performance of the proposed DFF against traditional DFFs and Dual Interlocked Storage Elements (DICEs) in terms of SEU immunity, area, and power consumption.

Main Methods:

• Introduction of an asymmetric scheme where the master-slave latch employs different hardening structures.
• Comparative analysis of the proposed DFF with traditional DFFs and DICE structures under identical operating conditions.
• Evaluation of SEU threshold, transistor count (area cost), and power consumption (average and peak).

Main Results:

• The proposed DFF exhibits an SEU threshold improvement of 10 times compared to traditional D flip-flops.
• The new structure requires six fewer transistors than the DICE structure, resulting in reduced area cost.
• Average and peak power consumption are reduced by 9.8% and 18.8% respectively, compared to DICE circuits.

Conclusions:

• The proposed asymmetric D flip-flop design offers significantly improved SEU tolerance.
• This DFF provides a favorable trade-off between circuit speed and SEU hardening, making it suitable for radiation-prone environments.
• The design demonstrates advantages in area and power efficiency over existing hardened flip-flop solutions like DICE.