Methodology for Testing Key Parameters of Array-Level Small-Area Hafnium-Based Ferroelectric Capacitors Using...

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Device Physics

Background:

• Hafnium-based ferroelectric memories offer enhanced integrated circuit performance but face endurance and retention challenges.
• Accurate, continuous testing of ferroelectric capacitor parameters is crucial for addressing these issues.
• Traditional measurement methods for ferroelectric capacitors are limited in timing, accuracy, and parasitic capacitance handling, especially for small-area devices.

Purpose of the Study:

• To analyze the working principles of ferroelectric capacitors.
• To design a novel method and circuit for detecting remnant polarization, saturation polarization, and imprint offset.
• To enable high-precision testing of ferroelectric capacitors, particularly small-area ones.

Main Methods:

• Analysis of ferroelectric capacitor working principles.
• Design of a test circuit incorporating a flip-readout circuit, capacitance calibration circuit, and VTC&TDC readout circuit.
• Simulation of the proposed circuit to evaluate its performance.

Main Results:

• The proposed circuit overcomes limitations of traditional methods, enabling high-precision ferroelectric capacitor testing.
• The capacitance calibration circuit achieved an 84% reduction in capacitance deviation.
• The readout circuit demonstrated 5.91 bits accuracy, 150 ns readout time, and 1 mW power consumption.

Conclusions:

• The developed circuit facilitates low-cost acquisition of array-level small-area ferroelectric capacitance data.
• This testing method can guide subsequent device optimization and circuit design for hafnium-based ferroelectric memories.
• The findings contribute to advancing the development of high-performance ferroelectric random-access memory (FeRAM).