Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications

Area of Science:

• Computer Engineering
• Hardware Architectures
• Low-Power Design

Background:

• Traditional network-on-chip (NoC) architectures often lack flexibility for dynamically reconfigurable intellectual properties (IPs).
• Static NoC designs can lead to suboptimal power consumption when IP demands fluctuate.
• Efficient resource sharing in Field-Programmable Gate Arrays (FPGAs) is crucial for modern embedded systems.

Purpose of the Study:

• To propose and evaluate two novel dynamically scalable NoC architectures for reconfigurable IPs.
• To demonstrate significant power reduction through runtime scalability.
• To develop a control manager for optimizing reconfiguration costs and resource utilization.

Main Methods:

• Development of a run-time scalable column-based NoC architecture.
• Extension to a second architecture with dynamic scaling of both rows and columns.
• Implementation and testing of prototypes on a Virtex 6 FPGA (ML605 board).
• Design of a control manager for IP and sub-NoC reconfigurations.

Main Results:

• Dynamically scalable NoC architectures achieve significant power reduction compared to static architectures.
• The proposed architectures effectively manage runtime scaling based on IP connectivity demands.
• Prototypes validated the feasibility and performance of the scalable NoC designs.

Conclusions:

• Dynamically scalable NoCs are highly effective for power saving in systems with reconfigurable IPs.
• The proposed architectures provide a flexible and efficient solution for resource sharing on FPGAs.
• This approach is beneficial for optimizing power and resource utilization in adaptive computing environments.