Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.

Area of Science:

• * Solid-state device physics
• * Semiconductor device engineering
• * Materials science

Background:

• * Single-port ferroelectric FETs (FeFETs) face limitations in tunable analog electronics due to read disturb, particularly in high-threshold voltage states.
• * The applied read bias in single-port FeFETs reduces the retention energy barrier, compromising data stability.
• * Existing FeFET architectures hinder broad application in advanced electronic systems.

Purpose of the Study:

• * To introduce a novel read disturb-free dual-port FeFET design.
• * To eliminate read disturb and improve the stability of FeFETs, especially in high-threshold voltage states.
• * To enable new applications in tunable analog electronics and Field-Programmable Gate Arrays (FPGAs).

Main Methods:

• * Development and theoretical analysis of a dual-port FeFET architecture.
• * Experimental validation using fully depleted silicon-on-insulator (FDSOI) FeFETs on a 22 nm platform.
• * Integration of a nonferroelectric dielectric layer for the read gate.

Main Results:

• * The dual-port FeFET design successfully eliminates read disturb by aligning the applied field with polarization or screening it with channel charge.
• * Improved stability in both high- and low-threshold voltage states was demonstrated.
• * Successful experimental demonstration of novel applications, including a frequency-tunable ring oscillator and FPGA prototypes.

Conclusions:

• * The proposed dual-port FeFET architecture offers a robust solution to the read disturb problem in FeFETs.
• * This design significantly enhances device stability and expands the applicability of FeFETs in advanced electronics.
• * The read disturb-free nature opens avenues for next-generation tunable analog circuits and memory applications.