Machine Learning Driven Channel Thickness Optimization in Dual-Layer Oxide Thin-Film Transistors for Advanced...

Area of Science:

• Materials Science
• Electrical Engineering
• Computer Science

Background:

• Machine learning (ML) offers adaptive learning for improved electronic device design.
• Optimizing complex multi-layer semiconductor structures presents significant challenges.
• Traditional design methods involve extensive trial-and-error, increasing time and cost.

Purpose of the Study:

• To apply Bayesian optimization (BO) for efficient design of dual-layer oxide semiconductor thin film transistors (OS TFTs).
• To manage interdependencies between semiconductor layers for optimized device characteristics.
• To simultaneously enhance field effect mobility (µ) and threshold voltage (Vth) while minimizing experimental efforts.

Main Methods:

• Utilized Bayesian optimization (BO) to model and optimize the dual-layer OS TFT structure.
• Integrated field effect mobility (µ) and threshold voltage (Vth) as key performance metrics.
• Employed a customized BO algorithm with adjustable weight factors for specific design preferences.

Main Results:

• Achieved a dual-layer OS TFT with enhanced field effect mobility of 36.1 cm² V⁻¹ s⁻¹.
• Demonstrated good operational stability under bias stress with minimal threshold voltage shift.
• Reduced experimental trials to only 15 data sets, showcasing significant efficiency gains.
• Successfully customized the BO model through weight factor adjustments for µ and Vth.

Conclusions:

• Bayesian optimization provides a powerful and efficient approach for designing advanced OS TFTs.
• The developed BO model effectively handles complex material interdependencies, leading to superior device performance.
• This methodology significantly reduces experimental workload and accelerates the development cycle for electronic devices.