Binary Neural Networks in FPGAs: Architectures, Tool Flows and Hardware Comparisons

Area of Science:

• Computer Science
• Artificial Intelligence
• Hardware Engineering

Background:

• Binary Neural Networks (BNNs) utilize binary weights {-1,1} for efficient computation.
• BNNs enable bitwise operations, accelerating training/inference and reducing hardware complexity.
• They are suitable for resource-constrained devices like FPGAs and ASICs, unlike traditional deep learning models.

Purpose of the Study:

• To provide a comprehensive review of Binary Neural Networks (BNNs) specifically for FPGA hardware implementation.
• To address the performance and accuracy trade-offs inherent in BNN binarization.
• To survey existing BNN architectures, design flows, and applications relevant to FPGAs.

Main Methods:

• Literature review of Binary Neural Network architectures and variants.
• Analysis of design and tool flows for implementing BNNs on FPGAs.
• Examination of BNN applications and benchmark results on FPGAs.

Main Results:

• BNNs offer significant advantages in speed and size reduction for hardware deployment.
• Binarization introduces a performance/accuracy tradeoff that researchers are actively mitigating.
• Various BNN architectures and FPGA implementation strategies have been developed.

Conclusions:

• BNNs are a promising approach for efficient deep learning on FPGAs.
• Further research is needed to close the performance gap between BNNs and full-precision networks.
• This review provides valuable insights into BNNs for FPGA hardware, including tools and benchmarks.