In-Depth Analysis on Self Alignment Effect of the Fermi-Level Using Graphene on Both n- and p-Type Semiconductors

Area of Science:

• Materials Science
• Semiconductor Physics
• Nanotechnology

Background:

• Optimizing transistor contact structures for reduced resistance is challenging.
• Existing methods struggle with integrating contacts for both n- and p-type semiconductors due to work function differences.
• This limitation hinders complementary metal-oxide-semiconductor (CMOS) technology advancement.

Purpose of the Study:

• To demonstrate a universal metal/graphene/semiconductor (MGrS) contact structure for both n- and p-type transistors.
• To address the limitations of current contact integration techniques in semiconductor devices.
• To improve the performance and integration capabilities of CMOS technology.

Main Methods:

• Fabrication and characterization of metal/graphene/semiconductor (MGrS) contact structures.
• Analysis of Schottky barrier height (SBH) and reverse current density (J_R).
• Investigation of graphene's role in mitigating Fermi level (FL) pinning and metal-induced gap states (MIGS).

Main Results:

• The MGrS structure significantly enhanced J_R and reduced SBH for both n- and p-type semiconductors.
• Graphene effectively alleviated FL pinning and reduced MIGS at the graphene/semiconductor interface.
• Excellent Ohmic contacts were achieved on Si substrates with ultra-low SBH values (0.012 eV for n-type, 0.024 eV for p-type).

Conclusions:

• The MGrS contact structure serves as a universal solution for n- and p-type transistors.
• Graphene's unique properties enable effective modulation of work functions and reduction of interface states.
• This approach offers extended capabilities for high-performance devices and CMOS circuitry.