In-Depth Analysis on Self Alignment Effect of the Fermi-Level Using Graphene on Both n- and p-Type Semiconductors

Optimizing the contact structure while reducing the contact resistance in advanced transistors has become an extremely challenging problem. Because the existing techniques are limited to controlling only one semiconductor type, either n- or p-type, owing to their work function differences, significant challenges are encountered in the integration of a contact structure and metal suitable for both n- and p-type semiconductors. This is a formidable drawback of the complementary metal-oxide-semiconductor (CMOS) technology. In this paper, we demonstrate the effectiveness of a metal/graphene/semiconductor (MGrS) as a universal source/drain contact structure for both n- and p-type transistors. The MGrS contact structure significantly enhanced the reverse current density (J_R) and reduced the Schottky barrier height (SBH) for both semiconductor types. From the analysis of the SBH values and their relationship with the metal work function, which refers to the S-parameter, the van der Waals contact of graphene (Gr) effectively alleviated the Fermi level (FL) pinning for both semiconductor types, reducing the metal-induced gap states (MIGS) at the Gr/semiconductor interface. Furthermore, Gr effectively modulated the work function of the contact metal to yield a position favorable for each semiconductor type. Consequently, a single MGrS contact structure on a Si substrate resulted in excellent Ohmic contacts in both n- and p-type Si, with SBH values reduced to 0.012 and 0.024 eV for n- and p-type Si, respectively. This new approach for integrating the contact structures of semiconductor types will lead to extended capabilities for high-performance device applications and CMOS logical circuitry.