The device performance limit of in-plane monolayer VTe₂/WTe₂ heterojunction-based field-effect transistors

Area of Science:

• Materials Science
• Condensed Matter Physics
• Nanotechnology

Background:

• Silicon-based field-effect transistors (FETs) face scaling limitations.
• Two-dimensional (2D) transition metal dichalcogenides (TMDs) offer potential alternatives for advanced electronics.
• VTe2/WTe2 heterojunctions are emerging as promising 2D materials for device applications.

Purpose of the Study:

• To investigate the transport properties of monolayer VTe2/WTe2 heterojunction-based FETs with double gates (DGs).
• To explore the device performance limits of these 2D FETs for future semiconductor technology nodes.
• To assess the feasibility of VTe2/WTe2 FETs for high-performance and low-power applications by 2028.

Main Methods:

• Utilizing an *ab initio* quantum transport approach for theoretical simulations.
• Modeling double-gate (DG) FETs with a 5 nm gate length (Lg).
• Simulating devices with varying underlap lengths (UL) and incorporating negative capacitance technology.

Main Results:

• DG-cold-source VTe2/WTe2 FETs with 5 nm Lg and 2-3 nm UL meet 2028 International Technology Roadmap for Semiconductors (ITRS) requirements for on-state current (Ion), power dissipation (PDP), and delay time (τ).
• Devices with 3 nm Lg and 2-3 nm UL also satisfy high-performance metrics for 2028 ITRS needs.
• Incorporating negative capacitance allows 1 nm Lg devices with 3 nm UL to meet 2028 high-performance targets.

Conclusions:

• 2D DG-cold-source VTe2/WTe2 FETs are viable candidates for next-generation electronics.
• Optimized underlap and gate configurations are crucial for achieving desired performance metrics.
• These 2D FETs show potential for driving Moore's Law scaling down to the 1 nm node.