A compact and efficient AES-32GF for encryption in small IoT devices.

Area of Science:

• Cryptography and Information Security
• Hardware Security
• Embedded Systems

Background:

• The proliferation of resource-constrained devices in Internet of Things (IoT) ecosystems necessitates efficient and secure information flow solutions.
• Existing cryptographic implementations often face challenges in balancing security, performance, and resource utilization on embedded platforms.

Purpose of the Study:

• To propose a compact and efficient Field-Programmable Gate Array (FPGA) implementation of the Advanced Encryption Standard (AES) with a 32-bit data-path, named AES-32GF.
• To minimize hardware resource consumption in FPGA implementations of AES through architectural optimizations.

Main Methods:

• Developed AES-32GF, an AES variant featuring a 32-bit data-path, implemented on Xilinx FPGAs.
• Employed data-path compression techniques to reduce the overall design footprint.
• Utilized Galois Field (GF) implementation for the S-box, a critical and resource-intensive component of AES.

Main Results:

• Achieved significant resource savings, with up to 87% reduction in slices compared to unrolled AES-128 architectures.
• Demonstrated high efficiency with AES-32GF achieving 3.37 Mbps/slice on an Artix-7 FPGA, alongside a throughput of 2.004 Gbps.
• The optimized S-box implementation and data-path compression led to minimized resource utilization (595 slices).

Conclusions:

• AES-32GF offers a compact and highly efficient solution for implementing AES encryption on FPGAs, suitable for resource-constrained IoT applications.
• The proposed design effectively minimizes resource consumption, outperforming existing designs in terms of cryptographic efficiency.
• This work contributes to enhancing the security of IoT devices without compromising hardware limitations.