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Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks.

Dario Fernandez Khatiboun, Yasser Rezaeiyan, Margherita Ronchini

    Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference
    |December 12, 2023
    PubMed
    Summary

    This study shows a feasible Field-Programmable Gate Array (FPGA) and 180nm CMOS circuit design for the biologically plausible supervised learning algorithm, Reconfigurable Spiking Neural Network (ReSuMe). The design features a configurable Spike-Timing-Dependent Plasticity (STDP) learning window for optimized neural network applications.

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    Area of Science:

    • Neuroscience
    • Computer Engineering
    • Artificial Intelligence

    Background:

    • Spiking Neural Networks (SNNs) are biologically inspired computational models.
    • Supervised learning algorithms are crucial for SNNs but often lack efficient hardware implementations.
    • Spike-Timing-Dependent Plasticity (STDP) is a key learning rule in SNNs.

    Purpose of the Study:

    • To demonstrate the feasibility of implementing a biologically plausible supervised learning algorithm, Reconfigurable Spiking Neural Network (ReSuMe), on hardware.
    • To design a configurable Spike-Timing-Dependent Plasticity (STDP) learning window for optimizing SNN performance.
    • To verify the integration capabilities of the ReSuMe algorithm with existing SNN structures.

    Main Methods:

    • FPGA implementation of the ReSuMe algorithm.
    • 180nm CMOS circuit design for the ReSuMe algorithm.
    • Development of a fully configurable STDP learning window function.

    Main Results:

    • Successful demonstration of FPGA implementation feasibility.
    • 180nm CMOS circuit design achieved with a core area of 0.78mm² at 1.8V.
    • Configurable STDP window verified for optimizing learning processes.

    Conclusions:

    • The ReSuMe algorithm is suitable for on-chip implementation in SNNs.
    • The designed hardware is capable of integration with various external SNN structures.
    • This work paves the way for efficient, hardware-accelerated biologically plausible learning in SNNs.