Search research articles

ABOUT JoVE

Overview Leadership Blog JoVE Help Center

AUTHORS

Publishing Process Editorial Board Scope & Policies Peer Review FAQ Submit

LIBRARIANS

Testimonials Subscriptions Access Resources Library Advisory Board FAQ

RESEARCH

JoVE Journal Methods Collections JoVE Encyclopedia of Experiments Archive

EDUCATION

JoVE Core JoVE Business JoVE Science Education JoVE Lab Manual Faculty Resource Center Faculty Site

Terms & Conditions of Use

Related Concept Videos

MOS Capacitor

MOS Capacitor

A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by

Same author

Base-Promoted <i>N-α-</i>C-H Alkylation of Aliphatic Amines via Tandem SET/1,5-HAT Processes.

Organic letters·2026

Same author

Acid-Base Responsive Carbon Nanodots Enabling Reversible Write-Erase Fluorescence Switching for Multilevel Anticounterfeiting.

ACS applied materials & interfaces·2026

Same author

Cd-Rich Shell-Engineered ZnCdS Nanocrystals for Ultrahigh-Performance Adjustable Shielding of Ultraviolet-Blue Light.

Journal of the American Chemical Society·2026

Same author

Risk factors for catheter-related complications after ultrasound-guided percutaneous transhepatic biliary drainage in malignant obstructive jaundice.

BMC surgery·2026

Same author

A nitride-based non-volatile memory enabled by electric-field-induced phase transition.

Nature materials·2026

Same author

Mussel-Inspired Magnetic Photothermal Superhydrophobic Sponge for Intelligent Oil Spill Cleanup.

Langmuir : the ACS journal of surfaces and colloids·2026

Search research articles

Related Experiment Video

Updated: Jul 8, 2025

A Fabrication and Measurement Method for a Flexible Ferroelectric Element Based on Van Der Waals Heteroepitaxy

A Fabrication and Measurement Method for a Flexible Ferroelectric Element Based on Van Der Waals Heteroepitaxy

Published on: April 8, 2018

Embedding security into ferroelectric FET array via in situ memory operation.

Yixin Xu¹, Yi Xiao¹, Zijian Zhao²

¹Pennsylvania State University, State College, PA, 16802, USA.

Nature Communications

|December 13, 2023

Summary

This summary is machine-generated.

This study introduces a novel, lightweight memory encryption method for non-volatile memories (NVMs). The new scheme significantly boosts encryption/decryption throughput and reduces latency, outperforming traditional Advanced Encryption Standard (AES) methods.

More Related Videos

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

Published on: May 13, 2020

Gradient Echo Quantum Memory in Warm Atomic Vapor

Gradient Echo Quantum Memory in Warm Atomic Vapor

Published on: November 11, 2013

Related Experiment Videos

Last Updated: Jul 8, 2025

A Fabrication and Measurement Method for a Flexible Ferroelectric Element Based on Van Der Waals Heteroepitaxy

A Fabrication and Measurement Method for a Flexible Ferroelectric Element Based on Van Der Waals Heteroepitaxy

Published on: April 8, 2018

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

Published on: May 13, 2020

Gradient Echo Quantum Memory in Warm Atomic Vapor

Gradient Echo Quantum Memory in Warm Atomic Vapor

Published on: November 11, 2013

Area of Science:

Computer Engineering
Memory Systems Security
Emerging Memory Technologies

Background:

Non-volatile memories (NVMs) offer advantages like low power and data retention but are vulnerable to security threats due to persistent data.
Existing NVM security solutions, often based on Advanced Encryption Standard (AES), introduce substantial performance and power overhead.
Ferroelectric Field-Effect Transistors (FeFETs) are a promising NVM technology, but their security implications require novel solutions.

Purpose of the Study:

To propose and validate a lightweight, in-situ memory encryption/decryption scheme for NVMs with minimal overhead.
To address the security vulnerabilities inherent in NVMs without compromising performance.
To demonstrate the effectiveness of the proposed scheme using FeFETs as a representative NVM technology.

Main Methods:

Developed a novel lightweight encryption/decryption scheme leveraging in-situ memory operations.
Conducted device-level and array-level experiments using ferroelectric field-effect transistors (FeFETs).
Performed comprehensive evaluations on a 128x128 FeFET AND-type memory array, analyzing area, latency, power, and throughput.

Main Results:

The proposed scheme achieved a ~22.6x and ~14.1x increase in encryption/decryption throughput compared to AES-based methods.
Negligible power penalty was observed, contrasting with the significant overhead of AES.
For neural network workloads, the scheme resulted in an average latency reduction of 90% for encryption and decryption processes.

Conclusions:

The proposed lightweight encryption scheme offers a highly efficient and secure solution for NVMs, particularly FeFETs.
This approach significantly enhances throughput and reduces latency, making it superior to AES-based security for NVM applications.
The findings pave the way for more secure and performant next-generation memory systems exploiting NVM properties.