Research on Convolutional Neural Network Inference Acceleration and Performance Optimization for Edge Intelligence.

Area of Science:

• Computer Science
• Artificial Intelligence
• Hardware Acceleration

Background:

• Edge intelligence (EI) integrates edge computing and AI, enabling AI algorithms on edge devices.
• Practical EI deployment is hindered by computational power, energy consumption, size, and cost constraints.
• Heterogeneous parallel computing platforms are essential for overcoming EI's performance-power trade-offs.

Purpose of the Study:

• To design and implement optimized hardware accelerators for deep learning on edge devices.
• To evaluate the performance and power efficiency of different optimization techniques for EI applications.
• To investigate the impact of quantization on FPGA resource utilization for EI.

Main Methods:

• Leveraged the Xilinx Zynq 7000 heterogeneous computing platform.
• Employed High-Level Synthesis (HLS) for accelerator design.
• Implemented and compared two LeNet-5 accelerators using loop unrolling and pipelining optimization techniques.

Main Results:

• The PIPELINE accelerator, at 100 MHz, showed a 14.972x speedup over the UNROLL accelerator with only an 8.09% increase in power consumption.
• Compared to a CPU, the PIPELINE accelerator achieved a 70.387x speedup and reduced power consumption by 91.37%.
• Compared to a GPU, the PIPELINE accelerator reduced power consumption by 93.35%.

Conclusions:

• Pipelining optimization offers superior performance for EI applications on FPGAs compared to loop unrolling.
• FPGA-based accelerators provide significant power and speed advantages over traditional CPUs and GPUs for EI.
• The study offers practical hardware acceleration schemes and insights into quantization effects for edge intelligence applications.