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Related Concept Videos

Upsampling01:22

Upsampling

238
Managing signal sampling rates is essential in digital signal processing to maintain signal integrity. A decimated signal, characterized by a reduced frequency range due to its lower sampling rate, can be upsampled by inserting zeros between each sample. This upsampling process expands the original spectrum and introduces repeated spectral replicas at intervals dictated by the new Nyquist frequency. To refine this zero-inserted sequence, it is passed through a lowpass filter with a cutoff...
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Signal processing techniques are essential for accurately converting continuous signals to digital formats and vice versa. When a continuous signal is sampled with a period T, the resulting sampled signal exhibits replicas of the original spectrum in the frequency domain, spaced at intervals equal to the sampling frequency. To handle this sampled signal, a zero-order hold method can be applied, which creates a piecewise constant signal by retaining each sample's value until the next...
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An Image Histogram Equalization Acceleration Method for Field-Programmable Gate Arrays Based on a Two-Dimensional

Yan Wang1, Peirui Liu1, Dalin Li1,2

  • 1Key Laboratory of Symbol Computation and Knowledge Engineering of Ministry of Education, College of Computer Science and Technology, Jilin University, Changchun 130012, China.

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|January 11, 2024
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Summary
This summary is machine-generated.

This study introduces a novel FPGA-based method for accelerating histogram equalization (HE) image processing. The two-dimensional pipeline architecture significantly boosts frame rates for real-time AI applications.

Keywords:
field-programmable gate arrays (FPGAs)hierarchical state machinehistogram equalizationtwo-dimensional pipeline

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Area of Science:

  • Computer Engineering
  • Image Processing
  • Artificial Intelligence

Background:

  • Real-time image processing demands are rising due to new AI applications like industrial detection and autonomous driving.
  • Histogram equalization (HE) is crucial for image quality but existing acceleration methods struggle with high frame rates.
  • Current HE acceleration on CPUs and embedded systems needs improvement for complex, high-speed scenarios.

Purpose of the Study:

  • To develop an efficient hardware acceleration method for histogram equalization (HE) on FPGAs.
  • To enhance the frame rate and performance of HE for demanding real-time AI applications.
  • To propose a novel two-dimensional configurable pipeline architecture for HE on FPGAs.

Main Methods:

  • Designed a two-dimensional configurable pipeline architecture to optimize HE parallelizability on FPGAs.
  • Adapted the HE algorithm to the hardware by enabling parallel cumulative histogram computation and simultaneous multi-input processing.
  • Optimized the pipeline and critical paths within the calculation units for higher operational frequency.

Main Results:

  • Achieved a maximum frequency of 891 MHz on a VCU118 test board.
  • Reached a frame rate of 1899 frames per second for 1080p images.
  • Demonstrated up to 22.6 times acceleration compared to CPU implementations.

Conclusions:

  • The proposed FPGA-based HE acceleration method effectively meets the high frame rate and low power demands of real-time AI.
  • The two-dimensional configurable pipeline architecture offers significant performance gains for image preprocessing.
  • This approach enables more complex and demanding AI applications requiring rapid image analysis.