Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines.

Area of Science:

• Integrated Circuits
• Computer Architecture
• Materials Science

Background:

• Field Programmable Gate Arrays (FPGAs) are crucial for accelerating deep learning due to their flexibility.
• Conventional FPGAs face limitations in balancing chip area and reconfiguration latency.
• Efficient dynamic reconfiguration for complex applications remains a challenge.

Purpose of the Study:

• To propose and validate a novel FPGA architecture using ferroelectric field-effect transistors (FeFETs).
• To enable efficient context-switching and dynamic reconfiguration without interrupting active operations.
• To overcome the inherent trade-offs in traditional FPGA designs.

Main Methods:

• Development of FeFET-based primitives for FPGA fabric (Look-Up Tables and Connection Blocks).
• Experimental verification of the proposed compact FPGA primitives.
• Evaluation of area, power consumption, critical path delay, and time savings.

Main Results:

• Significant reductions in Look-Up Table (LUT) area (63.0%) and Connection Block (CB) area (74.7%).
• Substantial decrease in CB (82.7%) and switch box (53.6%) power consumption.
• Minimal critical path delay penalty (9.6%) and considerable time savings for context-switching (78.7%) and dynamic reconfiguration (20.3%).

Conclusions:

• FeFET-based FPGAs offer a viable solution to overcome traditional design limitations.
• The proposed architecture achieves significant improvements in area, power efficiency, and reconfiguration speed.
• This technology paves the way for more efficient and dynamic hardware acceleration in deep learning and other applications.