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Chip-In-Loop SNN Proxy Learning: a new method for efficient training of spiking neural networks
Yuhang Liu1, Tingyu Liu1, Yalun Hu1
1SynSense Co. Ltd., Chengdu, China.
Frontiers in Neuroscience
|January 19, 2024
Summary
This study introduces Chip-In-Loop SNN Proxy Learning (CIL-SPL), a novel method to train spiking neural networks (SNNs). CIL-SPL overcomes performance loss in real-time asynchronous computation by bridging the gap between synchronous training and asynchronous hardware execution.
Area of Science:
- Artificial Intelligence
- Neuroscience
- Computer Engineering
Background:
- Current spiking neural network (SNN) training methods, including artificial neural network (ANN) conversion and direct surrogate gradient training, rely on frame-based computations.
- This frame-based approach creates a mismatch with the inherent asynchronous, event-driven nature of SNNs, leading to significant performance degradation on simulators and hardware.
- This degradation hinders the efficient deployment of SNNs for real-time applications.
Purpose of the Study:
- To propose and validate a hardware-based SNN proxy learning method, Chip-In-Loop SNN Proxy Learning (CIL-SPL).
- To eliminate the performance gap caused by the discrepancy between synchronous training methodologies and asynchronous SNN hardware execution.
- To demonstrate the efficacy of CIL-SPL in preserving model performance during real-time asynchronous computation.
Main Methods:
- Developed a novel hardware-based approach named Chip-In-Loop SNN Proxy Learning (CIL-SPL).
- Trained SNN models using CIL-SPL on public datasets, including N-MNIST.
- Evaluated the trained models on both SNN simulators and actual hardware chips to assess performance.
Main Results:
- CIL-SPL effectively mitigated the performance degradation typically observed when deploying frame-based trained SNNs onto asynchronous hardware.
- Models trained with CIL-SPL demonstrated comparable or improved performance on SNN simulators and hardware compared to classical training methods.
- The proposed method successfully addressed the synchronous-asynchronous computation mismatch.
Conclusions:
- Chip-In-Loop SNN Proxy Learning (CIL-SPL) offers a viable solution to the performance degradation issue in SNN deployment.
- This hardware-aware training approach enables more efficient and accurate real-time asynchronous computation with SNNs.
- CIL-SPL paves the way for more effective utilization of SNNs in edge computing and neuromorphic hardware applications.

