Parallel edge extraction operators on chip speed up photonic convolutional neural networks

Area of Science:

• Photonics
• Silicon Photonics
• Optical Computing

Background:

• Convolutional neural networks (CNNs) are crucial for image recognition.
• Efficient hardware for CNNs, especially for convolution operations, is needed.
• Photonic computing offers potential for high-speed, low-power computation.

Purpose of the Study:

• To develop a photonic multiplexing architecture for parallel edge extraction in CNNs.
• To enhance the speed and accuracy of image processing using silicon photonics.
• To demonstrate a novel approach for accelerating photonic convolution operations.

Main Methods:

• Experimental establishment of a 3x3 cross-shaped micro-ring resonator (MRR) array-based photonic multiplexing architecture.
• Implementation of parallel edge extraction operations using the MRR array.
• Evaluation of computability, energy efficiency, and accuracy on image datasets like CIFAR-10.

Main Results:

• Achieved a convolutional calculation speed up to four times faster by extracting four feature maps simultaneously.
• Demonstrated a maximum computability of 0.742 TOPS at an energy cost of 48.6 mW.
• Improved imaging recognition accuracy by 6.2% (reaching 78.7%) for the CIFAR-10 dataset using parallel edge extraction operators.

Conclusions:

• The proposed MRR array architecture enables highly scalable and efficient parallel edge extraction.
• This work presents a novel approach to significantly boost photonic computing speed for CNNs.
• The system demonstrates enhanced performance for image recognition tasks compared to universal operators.