New structure transistors for advanced technology node CMOS ICs

Area of Science:

• Electrical Engineering
• Materials Science
• Computer Engineering

Background:

• Integrated circuit (IC) advancements historically depended on transistor structural innovations.
• Transition from planar transistors to FinFET and GAAFET introduced 3D channels for improved control and performance.
• Geometrical scaling limitations beyond the 1-nm node necessitate new approaches for Moore's Law continuation.

Purpose of the Study:

• To review innovative works in transistor structure research and development for next-generation ICs.
• To highlight key process breakthroughs and design methodologies for advanced transistor architectures.
• To discuss future perspectives, including novel channel materials and operating principles.

Main Methods:

• Review of recent literature on transistor structural innovations.
• Analysis of vertical transistor stacking techniques like CFET, 3DS FETs, and VFETs.
• Exploration of shrinking cell sizes and advanced design methodologies.

Main Results:

• Vertical transistor stacking offers a revolutionary approach to IC scaling beyond geometrical limits.
• 3D channel architectures provide enhanced electrostatic integrity and higher operating currents.
• New transistor designs enable increased density and flexible circuit/system configurations.

Conclusions:

• Vertical transistor stacking is crucial for sustained IC development beyond the 1-nm node.
• Continued innovation in transistor structures, materials, and operating theories is essential.
• Advanced transistor designs pave the way for future high-performance integrated circuits.