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Analysis of Contact Interfaces for Single GaN Nanowire Devices
Published on: November 15, 2013
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Contacts at the Nanoscale and for Nanomaterials
Hei Wong1, Jieqiong Zhang2, Jun Liu2
1Department of Electrical Engineering, City University of Hong Kong, Hong Kong, China.
Nanomaterials (Basel, Switzerland)
|February 23, 2024
Summary
Contact resistance in nano complementary metal-oxide-semiconductor (CMOS) technology is a major challenge due to scaling. This review examines issues and methods for improving ohmic contacts in nano CMOS devices.
Area of Science:
- Materials Science
- Electrical Engineering
- Semiconductor Physics
Background:
- Scaling nano complementary metal-oxide-semiconductor (CMOS) devices presents significant challenges in contact resistance.
- Surface roughness, contact size, and film thicknesses exacerbate issues in nanometer-scale technology.
- Increased contact resistance and nonlinear current-voltage characteristics limit further device downsizing.
Purpose of the Study:
- To review challenges in contact size reduction for nano CMOS technology.
- To assess the validity of the Schottky junction model at the nanoscale.
- To examine difficulties in achieving transparent ohmic contacts with 2D materials.
Main Methods:
- Discussion of contact scaling issues in nano CMOS.
- Analysis of the Schottky junction model's nanoscale validity.
- Examination of challenges with 2D materials for ohmic contacts.
Main Results:
- Contact scaling issues increase resistance and nonlinearity in nano CMOS.
- Schottky junction model validity is questionable at the nanoscale.
- Achieving ohmic contacts with 2D materials faces hurdles like doping, band alignment, and Fermi-level pinning.
Conclusions:
- Addressing contact resistance is crucial for continued nano CMOS scaling.
- Novel approaches are needed to overcome limitations with 2D materials.
- Methods like van der Waals contacts, hybrid contacts, and buffer layers show promise for improving ohmic contacts.
