Polymeric Semiconductor in Field-Effect Transistors Utilizing Flexible and High-Surface Area Expanded...

Organic field-effect transistors (OFETs) were fabricated using three high-surface area and flexible expanded-poly(tetrafluoroethylene) (ePTFE) membranes in gate dielectrics, along with the semiconducting polymer poly[2,5-bis(2-octyldodecyl)pyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione-3,6-diyl)-alt-(2,2':5',2″:5″,2‴-quaterthiophen-5,5‴-diyl)] (PDPP4T). The transistor behavior of these devices was investigated following annealing at 50, 100, 150, and 200 °C, all sustained for 1 h. For annealing temperatures above 50 °C, the OFETs displayed improved transistor behavior and a significant increase in output current while maintaining similar magnitudes of V_th shifts when subjected to static voltage compared to those kept at ambient temperature. We also tested the response to NO₂ gas for further characterization and for possible applications. The ePTFE-PDPP4T interface of each membrane was characterized via scanning electron microscopy for all four annealing temperatures to derive a model for the hole mobility of the ePTFE-PDPP4T OFETs that accounts for the microporous structure of the ePTFE and consequently adjusts the channel width of the OFET. Using this model, a maximum hole mobility of 1.8 ± 1.0 cm²/V s was calculated for the polymer in an ePTFE-PDPP4T OFET annealed at 200 °C, whereas a PDPP4T OFET using only the native silicon wafer oxide as a gate dielectric exhibited a hole mobility of just 0.09 ± 0.03 cm²/V s at the same annealing condition. This work demonstrates that responsive semiconducting polymer films can be deposited on nominally nonwetting and extremely bendable membranes, and the charge carrier mobility can be significantly increased compared to their as-prepared state by using thermally durable polymer membranes with unique microstructures as gate dielectrics.